Integrated circuit devices, such as semiconductor chips, are commonly packaged using a lead frame and encapsulant material, such as a molding compound. For example, one or more semiconductor chips may be physically attached and electrically connected to a lead frame, e.g., using conductive bond wires. The encapsulant material is formed around the semiconductor chip and electrical connections. The encapsulant protects the semiconductor chip and electrical connections from damaging environmental conditions, such as moisture, temperature, foreign particles, etc. The leads of the lead frame are externally accessible from outside of the encapsulant material, and in some cases protrude away from the encapsulant material. These outer portions of the leads provide external electrical terminals that allow the packaged device to be electrically connected to a printed circuit board, for example.
Many semiconductor processing technologies utilize lead frame strips to simultaneously package a number of semiconductor devices. A lead frame strip includes a number of unit lead frames continuously repeated on a sheet conductor, with openings in the sheet conductor defining the features of the unit lead frames. Each unit lead frame provides the lead construction for a single packaged device. One or more semiconductor dies can be affixed to and electrically connected with each unit lead frame. The unit lead frames are singulated from one another to form individual packaged devices. The encapsulant material may be molded on the lead frame before or after the unit lead frames are singulated.
An important design consideration for many semiconductor applications is space efficiency. In many cases, the available space for a packaged semiconductor device is severely limited. Techniques for optimizing space efficiency include chip-stacking solutions. However, these techniques suffer from various drawbacks. For instance, direct slacking of chips within a package is limited by the available area of the die pad and the size of the semiconductor dies. Adequate cooling represents another challenge in these package styles, as only one of the two chips is in direct contact with the heat sink portion of the package (i.e., the die pad). Another solution involves the stacking of two distinct packaged semiconductor devices on top of one another. With stacked packaged devices, electrical interconnection between the two devices represents a notable challenge. Electrical connection between the two devices can be done using a so-called interposer. However, this interposer adds cost, complexity and increases the overall thickness of the design.